Asymmetric sense amplifier
US8027214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Dec 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.