Apparatus and method for transferring a signal from a fast clock domain to a slow clock domain
US8027420B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Jun 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit is provided for transferring a signal from a fast clock domain to a slow clock domain. The circuit includes a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal. The circuit also a slow clock domain configured to receive the transferred intermediate signal from the fast clock domain and, responsively, generate an output signal. The circuit further includes a first synchronizer disposed in the slow clock domain and a second synchronizer disposed in the fast clock domain. The first synchronizer, operating with a slow clock, is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal. The second synchronizer, operating with a fast clock, is configured to receive a feedback signal from the first synchronizer for acknowledging synchronization of the output signal to the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.