Method and apparatus for synchronizing processors in a hardware emulation system
US8027828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Sep 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and method for compiling a hardware design for performing hardware emulation using synchronized processors is described. The apparatus comprises a plurality of processors defining a processor group for evaluating data regarding a hardware design and a synchronizer for synchronizing the operation of the processor group while emulating at least a portion of the hardware design. The method comprises providing a synchronization signal to a plurality of processors defining a processor group for evaluating data regarding a hardware design, receiving a ready signal from the processor group, and providing an execution signal to the processor group, where the execution signal causes the processor group to evaluate a submodel. The method for compiling the hardware design comprises converting at least one high-level construct into a sequence of operations and identifying a sequence of operations that comprise at least one conditional submodel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.