Method and system for reducing instruction storage space for a processor integrated in a network adapter chip
US8028154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2005 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Jul 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/328
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.