Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
US8028181B2 · kind B2 · utility
1Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Mar 25, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.