Scalable scan system for system-on-chip design
US8028209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Dec 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improve the scan test coverage of the system-on-chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.