Interleaving scheme for an LDPC coded 16APSK system
US8028219B2 · kind B2 · utility
8Cited by
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3Claims
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Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Sep 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2053
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.