System and method for improved placement in custom VLSI circuit design with schematic-driven placement
US8028265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Dec 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.