Method for determining time to failure of submicron metal interconnects
US8030099B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | May 11, 2005 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | May 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/287
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The test structure is arranged such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection. From these measurements, time to failure characteristics are determined, whereby the change in the test conditions is compensated for.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.