Semiconductor device and method of manufacturing the same
US8030204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Nov 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.