Bonding method for through-silicon-via based 3D wafer stacking
US8030208B2 · kind B2 · utility
13Cited by
13References
11Claims
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Key dates
| Filing date | Jun 2, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Aug 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.