Patent · US Active

Semiconductor memory device

US8030662B2 · kind B2 · utility

6Cited by

4References

2Claims

0Family size

Assignee

NATIONAL UNIVERSITY ORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY · JP

Inventor

Yoshiyuki Suda · Koganei, JP

Key dates

Filing date	Sep 8, 2008
Grant date	Oct 4, 2011
Priority date	—
Expiry date	Sep 8, 2028

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S438/931
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.