Method for continuity test of integrated circuit
US8030944B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Sep 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/54
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention provides a method for continuity test of integrated circuit. By using both pins of integrated circuit to measure a current of an electrostatic discharge device, the contact resistance of the integrated circuit can be obtained by calculating. The method comprises the steps: First, a DUT (device under test) is provided, and the DUT includes a second pin and the second pin connecting zero reference potential. Then, a voltage is applied to a first pin of DUT. Finally, the current through said first pin and said second pin would be measured. Therefore, the testing result of the DUT could be more precise and the quality of the DUT would be made sure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.