Patent · US Active

Systems and methods using improved clock gating cells

US8030982B2 · kind B2 · utility

24Cited by

3References

23Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Animesh Datta · San Diego, US
Martin Saint-Laurent · Austin, US
Varun Verma · Newcastle, US
Prayag Bhanubhai Patel · San Diego, US

Key dates

Filing date	Oct 30, 2008
Grant date	Oct 4, 2011
Priority date	—
Expiry date	Dec 14, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0013
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.