Circuit for clock extraction from a binary data sequence
US8030984B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2007 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Apr 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting the transition edges of the binary sequence producing a brief pulse at each transition, a sampler (MLT) for tapping off the level of the sinusoidal voltage at the instant of the brief pulse, and an integrator (AOP, R1, C1) for integrating this level in tandem with the successive pulses, the output of the integrator being applied as control voltage to the oscillator with controlled frequency, the output of the oscillator being the desired clock frequency with a slaved phase passing through zero substantially in the middle of the interval between two binary data transitions. Such a circuit is useful in applications for transmitting digital data of serial type, in which the data are received without at the same time receiving a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.