PLL with loop bandwidth calibration circuit
US8031008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2009 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Jun 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.