Stacked memory module and system
US8031505B2 · kind B2 · utility
41Cited by
5References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2009 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Aug 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.