Multi-path accessible semiconductor memory device with prevention of pre-charge skip
US8032695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Jun 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.