Non-volatile semiconductor storage device and non-volatile storage system
US8032810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2007 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Aug 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.