SIC power DMOSFET with self-aligned source contact
US8035112B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jul 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermediate product in the fabrication of a MOSFET, including a silicon carbide wafer having a substrate and a drift layer on said substrate, said drift layer having a plurality of source regions formed adjacent an upper surface thereof; a first oxide layer on said upper surface of said drift layer; a plurality of polysilicon gates above said first oxide layer, said plurality of polysilicon gates including a first gate adjacent a first of said source regions; an oxide layer over said first source region of greater thickness than said first oxide layer; and, an oxide layer over said first gate of substantially greater thickness than said oxide layer over said first source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.