Signal sampling circuit
US8035539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Sep 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sampling circuit includes multiple sampling channels adapted to sample the signal in time-multiplexed fashion. Each sampling channel includes a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. In an embodiment, the holding time period includes a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.