Memory module for improving signal integrity and computer system having the same
US8036011B2 · kind B2 · utility
6Cited by
2References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 18, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Dec 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes a plurality of buses and a plurality of memory chips arranged close to each other along each of the plurality of buses. An N-th memory chip, where N is an integer, of the plurality of memory chips is connected to any one of the plurality of buses, and each of the other memory chips of the plurality of memory chips, except for the N-th memory chip, is connected to the other one of the plurality of buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.