Patent · US Active

5T high density NVDRAM cell

US8036032B2 · kind B2 · utility

7Cited by

66References

16Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Andreas Scade · Dresden, DE
Stefan Guenther · Lake Orion, US

Key dates

Filing date	Dec 31, 2007
Grant date	Oct 11, 2011
Priority date	—
Expiry date	Jun 25, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C14/0018
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.