Physical layer transceiver with integrated time synchronization
US8036202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2006 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jun 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed, inter alia, is a Physical Layer Transceiver (PHY) with integrated time synchronization, such as, but not limited to, IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The PHY includes circuitry to maintain a current time, and to trigger the storage of timestamps corresponding to received frames. Typically, in response to a request from an external device, the timestamps are retrieved from storage and are communicated to the external device. By moving the triggering of the storage of the timestamps by the PHY itself, rather than by a monitoring of the traffic between the PHY and the Media Access Controller (MAC), higher accuracy can typically be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.