QOS aware expansion mechanism
US8036228B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 2004 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jun 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data communication system comprising a plurality of peripherals having respective interfaces, the interfaces having device drivers and being coupled to a common bus for communication with a management system, the interfaces having different real time requirements; an ATM SAR and scheduler employs a predefined PHY level interface with different levels of service, the PHY interface being used as a QOS (Quality of Service) aware common master-slave bus for the peripherals which act as slave devices, whereby respective device driver requirements can be simplified or eliminated. A predefined PHY level interface is the ATM Forum UTOPIA, each peripheral being addressed as a separate UTOPIA slave port. The invention discloses how a system required to support interfaces with differing real time requirements may be supported through the use of a common bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.