Dual loop clock recovery circuit
US8036300B2 · kind B2 · utility
117Cited by
13References
34Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 11, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jun 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.