Apparatus and method for micro performance tuning of a clocked digital system
US8037340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2007 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jun 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.