System and method for validating channel transmission
US8037356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2007 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jan 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.