Techniques for generating bit reliability information in a post-processor using an error correction constraint
US8037394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Aug 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/1863
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.