Data aligner in reconfigurable computing environment
US8037439B2 · kind B2 · utility
0Cited by
13References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Apr 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/45
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.