Optimization of ROM structure by splitting
US8037440B2 · kind B2 · utility
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7Claims
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Key dates
| Filing date | Jul 20, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Apr 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.