Method for shape and timing equivalent dimension extraction
US8037575B2 · kind B2 · utility
10Cited by
29References
18Claims
0Family size
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Key dates
| Filing date | Sep 16, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Jul 7, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.