Passivated tiered gate structure transistor

US8039903B1 · kind B1 · utility

Assignee

• HRL Laboratories, LLC · US

Inventors

• Ivan Milosavljevic · Thousand Oaks, US
• Adele Schmitz · Thousand Oaks, US
• Michael Antcliffe · Los Angeles, US
• Ming Hu · Beijing, CN
• Lorna Hodgson · Cornelius, US

Key dates

• Filing date: Sep 3, 2009
• Grant date: Oct 18, 2011
• Expiry date: Sep 3, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head.