Low-dropout voltage regulator with level limiter limiting level of output voltage when level of load current changes and method of operating the same
US8040118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/779
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A low-dropout (LDO) voltage regulator that includes an error amplifier which compares a reference voltage with a feedback voltage of an output voltage and outputs an error signal based on the result of the comparison, the error amplifier being biased by an input voltage; a first MOS transistor having a gate electrically connected to the error signal, a source electrically connected to the input voltage and a drain electrically connected to the output voltage; a voltage divider which transmits a predetermined part of the output voltage to the error amplifier as feedback voltage; and a level limiter which limits a level of the output voltage from changing beyond and below an offset voltage when a level of a load current changes. In accordance with embodiments, A predetermined number of comparators and MOS transistor type-switches are provided to enhance the slew ratio of the regulated output voltage and to reduce standby electricity consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.