Separate configuration of I/O cells and logic core in a programmable logic device
US8040152B1 · kind B1 · utility
6Cited by
6References
12Claims
0Family size
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Key dates
| Filing date | Feb 2, 2010 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Feb 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) is provided that includes: a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the plurality of programmable logic blocks; a plurality of input/output (I/O cells), each I/O cell associating with a corresponding set of I/O configuration memory cells; and a plurality of boundary scan cells corresponding to the plurality of I/O cells, each boundary scan being configurable to form a second data shift register for the I/O configuration memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.