Lock detection circuit and lock detecting method
US8040156B2 · kind B2 · utility
9Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Jul 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.