Analog-to-digital conversion in pixel array
US8040269B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | May 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter generates an output digital value equivalent to the difference between two analog signals. The converter forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock is dedicated to the converter, or a sub-set of converters. A control stage enables a first counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters. A-to-D conversion can include a first A-to-D conversion stage which determines a signal range, selected from a plurality of signal ranges, and a second A-to-D conversion stage which determines an M-bit digital value equivalent to the difference between the first and second analog signals by comparing the signals with a ramp signal, with the ramp signal having the signal range determined by the first analog-to-digital conversion stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.