Thin film transistor array panel and manufacturing method of the same
US8040449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | May 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel includes a substrate; a gate electrode formed on the substrate; a data line formed on the substrate; a gate insulating layer formed on the data line and the gate electrode, and having a first contact hole exposing the gate electrode, and a second contact hole exposing the data line; a gate line intersecting the data line, and connected to the gate electrode through the first contact hole; a semiconductor formed the gate insulating layer, and including a channel of a thin film transistor; a source electrode connected to the data line through the second contact hole; a drain electrode opposite to the source electrode with respect to the channel on the semiconductor; a passivation layer having a third contact hole exposing the drain electrode; and a pixel electrode connected to the drain electrode through the third contact hole are included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.