Semiconductor memory arrangement
US8040710B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2007 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Aug 10, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.