Dual mode memory system for reducing power requirements during memory backup transition
US8040750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Sep 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.