Method, system and apparatus for reducing memory traffic in a distributed memory system
US8041898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.