High-speed semiconductor memory test device
US8042015B2 · kind B2 · utility
3Cited by
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16Claims
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Inventor
Key dates
| Filing date | Jun 11, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Oct 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference clock signal, a clock converting unit receiving the reference clock signal and converting the frequency of the reference clock signal to a second clock signal in response to the control signal, and a test data converting unit receiving the first test data, converting the first test data to second test data synchronously with the second clock signal and providing the second test data to a semiconductor memory device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.