Memory system with cyclic redundancy check
US8042023B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one block of data signals to be transferred, and at least one cyclic redundancy checksum calculator included in one of the memory controller and the memory module, the calculators being configured to calculate a cyclic redundancy checksum for the at least one data signal block, wherein the pre-stored address signal is used as an initial value for the calculation of the cyclic redundancy checksum and the at least one block of data and address signals are transferred together with the calculated cyclic redundancy checksum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.