Four-stage pipeline based VDSL2 Viterbi decoder
US8042032B2 · kind B2 · utility
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5References
10Claims
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Key dates
| Filing date | Dec 21, 2006 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Oct 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/256
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel method to divide the whole decoding process of the Viterbi decoder into four pipeline stages and the Viterbi decoder therefore. With an appropriate choice on the system clock, the invention trade-off the decoding speed with the hardware cost so that the designed Viterbi decoder is able to satisfy the decoding speed requirement for the highest speed profile in VDSL2 systems, 30 MHz profile. At the same time, with four-stage pipeline to just enough to meet the speed requirement, the hardware cost for the new designed Viterbi decoder is reduced compared with single-staged decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.