Method of fabricating semiconductor device having multiple gate insulating layer
US8043916B2 · kind B2 · utility
1Cited by
5References
10Claims
0Family size
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Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.