Method of fabricating semiconductor device
US8043922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Jan 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/44
Abstract
A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.