Integrated circuit cell architecture configurable for memory or logic elements
US8044437B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2005 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Jan 5, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.