Nonvolatile semiconductor memory device and producing method thereof
US8044456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2009 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Jan 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
Abstract
A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.