Thin film transistor array panel and manufacturing method thereof
US8045105B2 · kind B2 · utility
0Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2009 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | May 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0241
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor substrate according to one or more embodiments of the present invention includes a gate line formed on a substrate, a data line that is insulated from and intersects the gate line, a thin film transistor connected to the gate line and the data line, a barrier rub formed on the thin film transistor and partitioning a plurality of first openings, a reflecting electrode formed in each of the first openings, and a pixel electrode formed on the reflecting electrode and that is electrically connected to the thin film transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.