Semiconductor memory device
US8045389B2 · kind B2 · utility
2Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Nov 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.